Data transmission is an important application of many integrated circuit devices. Data may be transmitted according to different transmission protocols, and may be transmitted as serial data or parallel data. Data may also be transmitted within a circuit between registers (e.g., flip-flops), such as through combinatorial logic or programmable elements. Because the transmission speed of data is important, the layout of circuit elements in paths that transmit data is important. Certain circuits may depend upon a number of paths that are provided in parallel, where the timing of receiving data is important. One way to improve the speed of the transmission of data in a circuit is to provide pipelining.
Conventional pipelining techniques typically formulate a linear programming (LP) retiming problem and solve it for a specified maximum frequency to minimize register count. One problem with this type of technique is that it includes runtimes that grow exponentially with the number of paths in the design. Conventional pipelining techniques assume an infinite number of registers are available and, when applied to FPGAs, could saturate the available registers (either locally or globally) before finishing an iteration. Further, some of the most critical signals may not be pipelined. Conventional techniques also attempt to solve the entire problem in one iteration without changing placement intermediately, leading to a larger number of registers required to meet a given cycle time, or where the cycle time may not be met.